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CY7C1020CV33
512K (32K x 16) Static RAM
Features
* Pin- and function-compatible with CY7C1020V33 * Temperature Ranges -- Commercial: 0C to 70C -- Industrial: -40C to 85C -- Automotive: -40C to 125C * High speed -- tAA = 10 ns * CMOS for optimum speed/power * Low active power -- 325 mW (max.) * Automatic power-down when deselected * Independent control of upper and lower bits * Available in Pb-free and non Pb-free 44-pin TSOP II package
Functional Description
The CY7C1020CV33 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1020CV33 is available in standard 44-pin TSOP Type II package.
Logic Block Diagram
DATA IN DRIVERS
Pin Configuration[1]
TSOP II Top View NC A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A4 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A7 A6 A5 A4 A3 A2 A1 A0
32K x 16 RAM Array
I/O1-I/O8 I/O9-I/O16
COLUMN DECODER BHE WE CE OE BLE
A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC
ROW DECODER
Note: 1. NC pins are not connected on the die
Cypress Semiconductor Corporation Document #: 38-05133 Rev. *E
A8 A9 A10 A11 A12 A13 A14
*
SENSE AMPS
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised August 3, 2006
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CY7C1020CV33
Selection Guide
-10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Com'l/Ind'l Automotive Com'l/Ind'l Automotive 10 90 5 -12 12 85 5 -15 15 80 85 5 10 Unit ns mA mA mA mA
Pin Definitions
Pin Name A0-A14 I/O1-I/O16 NC WE CE BHE, BLE OE TSOP - Pin Number 5, 4, 3, 2, 18, 44, 43, 42, 27, 26, 25, 24, 21, 20, 19 7-10, 13-16, 29-32, 35-38 1, 22, 23, 28 17 6 40, 39 41 I/O Type Input Description Address Inputs used to select one of the address locations.
Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation. No Connect No Connects. Not connected to the die. Input/Control Write Enable Input, active LOW. When selected LOW, a Write is conducted. When deselected HIGH, a Read is conducted. Input/Control Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Input/Control Byte Write Select Inputs, active LOW. BHE controls I/O16-I/O9, BLE controls I/O8-I/O1. Input/Control Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. Ground Ground for the device. Should be connected to ground of the system.
VSS VCC
12, 34 11, 33
Power Supply Power Supply inputs to the device.
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CY7C1020CV33
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ....................................-0.5V to VCC + 0.5V DC Input Voltage .................................-0.5V to VCC + 0.5V
[2]
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA
Operating Range
Range Commercial Industrial Automotive Ambient Temperature 0C to +70C -40C to +85C -40C to +125C VCC 3.3V 10% 3.3V 10% 3.3V 10%
Electrical Characteristics Over the Operating Range
-10 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current GND < VI < VCC Com'l/Ind'l Auto Com'l/Ind'l Auto Com'l/Ind'l Auto 15 15 90 85 -1 +1 -1 +1 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 Min. 2.4 0.4 VCC + 0.3 0.8 +1 2.0 -0.3 -1 Max. Min. 2.4 0.4 VCC + 0.3 0.8 +1 2.0 -0.3 -1 -20 -1 -20 -12 Max. Min. 2.4 0.4 VCC + 0.3 0.8 +1 +20 +1 +20 80 85 15 20 5 5 5 10 -15 Max. Unit V V V V A A A A mA mA mA mA mA mA
Output Leakage GND < VI < VCC, Current Output Disabled VCC Operating VCC = Max., Supply Current IOUT = 0 mA, f = fMAX = 1/tRC Automatic CE Power-down Current --TTL Inputs Automatic CE Power-down Current --CMOS Inputs
ISB1
Max. VCC, CE > VIH Com'l/Ind'l VIN > VIH or VIN < VIL, Auto f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Com'l/Ind'l Auto
ISB2
Capacitance[3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF
Thermal Resistance[3]
Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 44-pin TSOP-II 76.92 15.86 Unit C/W C/W
JA JC
Notes: 2. VIL (min.) = -2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05133 Rev. *E
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CY7C1020CV33
AC Test Loads and Waveforms[4]
R 317 3.3V OUTPUT 30 pF R2 351 GND 3.0V 90% 10% ALL INPUT PULSES 90% 10% High-Z characteristics: R 317 3.3V OUTPUT 5 pF
Rise Time: 1 V/ns
(a)
(b)
Fall Time: 1 V/ns
R2 351
(c)
Switching Characteristics Over the Operating Range[4]
-10 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU[7] tPD[7] tDBE tLZBE tHZBE Write Cycle[8] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z
[5]
-12 Max. Min. 12 10 12 3 10 5 12 6 0 5 6 3 5 6 0 10 5 12 6 0 5 6 12 9 8 0 0 8 6 0 3 5 6 8 9 15 10 10 0 0 10 8 0 3 0 0 3 0 3 Max. Min. 15
-15 Max. Unit ns 15 15 7 7 7 15 7 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 ns ns
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to OE HIGH to CE HIGH to Low-Z[5] High-Z[5, 6]
Min. 10 3
0 3 0
CE LOW to Low-Z[5] High-Z[5, 6] CE LOW to Power-up CE HIGH to Power-down Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z
0
10 8 7 0 0 7 5 0 3 7
WE LOW to High-Z[5, 6] Byte Enable to End of Write
Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. This parameter is guaranteed by design and is not tested. 8. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
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CY7C1020CV33
Switching Waveforms
Read Cycle No. 1[9, 10]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[10, 11]
ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB IICC CC tHZOE
HIGH IMPEDANCE
DATA OUT
Notes: 9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 10. WE is HIGH for Read cycle. 11. Address valid prior to or coincident with CE transition LOW.
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CY7C1020CV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[12, 13]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE tBW BHE, BLE tSD DATA I/O tHD
tHA
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATA I/O tHD
tHA
Notes: 12. Data I/O is high impedance if OE or BHE and/or BLE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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CY7C1020CV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC ADDRESS
CE
tSCE
tAW tSA tPWE
tHA
WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD
Truth Table
CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O1-I/O8 High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z High-Z I/O9-I/O16 High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z High-Z Power-down Read--All bits Read--Lower bits only Read--Upper bits only Write--All bits Write--Lower bits only Write--Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 10 12 15 Ordering Code CY7C1020CV33-10ZC CY7C1020CV33-10ZXC CY7C1020CV33-12ZC CY7C1020CV33-15ZC CY7C1020CV33-15ZE CY7C1020CV33-15ZSXE Package Diagram 51-85087 Package Type 44-pin TSOP Type II 44-pin TSOP Type II (Pb-Free) 44-pin TSOP Type II 44-pin TSOP Type II 44-pin TSOP Type II 44-pin TSOP Type II (Pb-Free) Commercial Commercial Automotive Operating Range Commercial
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CY7C1020CV33
Package Diagrams
44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH) MAX MIN.
22 1
PIN 1 I.D.
11.938 (0.470) 11.735 (0.462)
10.262 (0.404) 10.058 (0.396)
OR E KXA SG
23
44
EJECTOR PIN
TOP VIEW
BOTTOM VIEW
0.800 BSC (0.0315)
0.400(0.016) 0.300 (0.012)
BASE PLANE 0-5 0.10 (.004)
10.262 (0.404) 10.058 (0.396) 0.210 (0.0083) 0.120 (0.0047)
18.517 (0.729) 18.313 (0.721) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) SEATING PLANE
0.597 (0.0235) 0.406 (0.0160)
51-85087-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1020CV33
Document History Page
Document Title: CY7C1020CV33 512K (32K x 16) Static RAM Document Number: 38-05133 REV. ** *A *B *C *D *E ECN NO. 109428 115045 117615 262949 334398 493543 Issue Date 12/16/01 05/30/02 08/14/02 See ECN See ECN See ECN Orig. of Change HGK HGK DFP RKF SYT NXR New Data Sheet ICC and ISB1 data modified Pin 1= NC Pin 18 = A4; remove SOJ package option; remove 8ns option. Added Automotive Specs to Data sheet Added Lead-Free Product Information Added note #1 on page #1 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated Ordering Information Table Description of Change
Document #: 38-05133 Rev. *E
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